View AX88178_1388415.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asix electronics corporation released date: 4/16/2004 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http:// www.asix.com.tw AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller features ? single chip usb to 10/100/1000 gigabit ethernet and homepna and homeplug network controller ? usb specification 1.0 and 1.1 and 2.0 compliant ? supports usb full and high speed modes with bus power capability ? supports 4 endpoints on usb interface ? high performance packet transfer rate over usb bus using proprietary burst transfer mechanism (submitted for us patent application) ? ieee 802.3, 802.3u, and 802.3ab (10base-t, 100base-tx, and 1000base-t) compatible ? embedded 20kb sram for rx packet buffering and 20kb sram for tx packet buffering ? supports both full-duplex and half-duplex operation in fast ethernet ? provides mii/gmii/rgmii in terfaces for ethernet phy interface and mii interface for homepna/ homeplug phy interface ? supports jumbo packet of up to 9kb ? supports suspend mode and remote wakeup via link-up, magic packet, or external pin ? optional phy power down during suspend mode ? supports 256/512 bytes (93c56/93c66) of serial eeprom (for storing usb descriptors) ? supports automatic loading of ethernet id, usb descriptors and adapter configuration from eeprom after power-on initialization ? external phy loop-back diagnostic capability ? integrates on-chip 3.3v to 2.5v voltage regulator and requires only single power supply: 3.3v ? small form factor with 128-pin lqfp package ? 12mhz clock input from either crystal or oscillator source *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the AX88178 usb to 10/100/1000 gigabit ethernet/homepna/homeplug controller is a high performance and highly integrated asic with embedded 40kb sram for packet bufferi ng. it enables low cost and affordable gigabit ethernet network connection to desktop and not ebook pc using popular usb ports that are built-in to many pc today. it has an usb interface to communicate with usb host controller and is compliant with usb specificati on v1.0, v1.1 and v2.0. it implements 10/100/1000mbps et hernet lan function based on ieee802.3, ieee802.3u, ieee802.3ab standards or homepna standard. it supports media-i ndependent interface (mii) to simplify the design on implementi ng fast ethernet and homepna functions. it al so provides gigabit media-i ndependent (gmii) and reduced gigabit media-independent (rgmii) interface for interfacing w ith gigabit ethernet phy. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electr onics reserves the rights to m odify product speci fication without notice. no liability is assumed as a result of the us e of this product. no rights under any pa tent accompany the sale of the product. AX88178 10/100/1000 gigabit ethernet phy ma g netic r j 45 usb i/f eeprom 1/10 mbps home lan phy ma g netic r j 11 document no: AX88178-02/4/20/2004
asix electronics corporation 2 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller table of contents 1.0 introduct ion .....................................................................................................3 2.0 signal des cription..........................................................................................5 3.0 function des cription .....................................................................................8 4.0 serial eeprom me mory map .........................................................................9 5.0 usb configuration struct ure .................................................................13 6.0 usb comm ands.................................................................................................14 7.0 electrical spec ification s .........................................................................25 8.0 package info rmation...................................................................................32 9.0 ordering in formation .................................................................................33 appendix a: system applicat ions ........................................................................33 revision hi story .........................................................................................................35 list of figures f igure 1: AX88178 b lock d iagram ................................................................................................3 f igure 2: AX88178 p inout d iagram ................................................................................................4 f igure 3: m ulticast f ilter e xample ............................................................................................20 list of tables t able 1: p inout d escripton .............................................................................................................5 t able 2: s erial eeprom m emory m ap .........................................................................................9 t able 3: usb s tandard c ommand r egister m ap .......................................................................14 t able 4: usb v endor c ommand r egister m ap ..........................................................................15 t able 5: r emote w akeup t ruth t able ........................................................................................24
asix electronics corporation 3 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 1.0 introduction 1.1 general description the AX88178 usb to 10/100/1000 gigabit ethernet/homepna/homeplug controller is a high performance and highly integrated asic with embedded 40kb sram for packet bufferi ng. it enables low cost and affordable gigabit ethernet network connection to desktop and not ebook pc using popular usb ports that are built-in to many pc today. it has an usb interface to communicate with usb host controller and is compliant with usb specificati on v1.0, v1.1 and v2.0. it implements 10/100/1000mbps et hernet lan function based on ieee802.3, ieee802.3u, ieee802.3ab standards or homepna standard. it supports media-i ndependent interface (mii) to simplify the design on implementi ng fast ethernet and homepna functions. it al so provides gigabit media-i ndependent (gmii) and reduced gigabit media-independent (rgmii) interface for interfacing w ith gigabit ethernet phy. the AX88178 needs 12mhz clock for usb operation and 125mhz cl ock for gigabit ethernet operation. it is in 128-pin lqfp low profile package with cmos process and requires only single 3.3v power supply to operate. 1.2 AX88178 block diagram figure 1: AX88178 block diagram gpio2~0 gigabit mac core memory arbiter usb to ethernet bridge usb core and interface sta seeprom loader i/f dp/dm dprs/dmrs mii/gmii/rgmii i/f mdc mdio eecs eeck eedi eedo 40kb sram general pur p ose i/o
asix electronics corporation 4 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 1.3 AX88178 pinout diagram the AX88178 is housed in the 128-pin lqfp package. figure 2: AX88178 pinout diagram int_regulator_en 12345678910111213141516 33 34 35 36 37 38 39 40 41 42 43 asix AX88178 17 18 19 20 44 45 46 47 21 22 23 24 25 48 49 50 51 52 53 54 55 56 57 26 27 28 29 30 31 32 58 110 109 108 107 106 103 104 105 117 116 115 114 111 112 113 124 123 122 121 118 119 120 128 125 126 127 59 60 61 62 63 64 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 102 101 98 99 100 97 dmrs gnd vddk vbus testspeedup nc forcefs_n extwakeup_n gndah vdd3 scan_test scan_enable clk60ext clksel vddk gnd eeck eecs eedi eedo vdd3 v25 agnd avdd3 tx_clk tx_en gtx_clk txc tx_er txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 gnd avddk xin125m rgmii_en agnd vdd3 gnd vdd2 agnd avddk db avddk agnd nc nc agnd nc nc nc nc vddk nc nc gnd vdd2 vdd2 rx_clk rx_dv rx_er rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs col gnd mdint mdc mdio gpio0 gpio1 gpio2 gnd vdd3 phyrst_n nc nc nc nc nc usb_speed_led led gnd vddk dp dm gnd gnd vddk reset_n vddah gnd gnd xin12m xout12m avdd3 agnd rref agnd rpu dprs avdd3 gnd vdd3 nc nc avddk agnd agnd avddk avddk agnd nc nc nc hs_test_mode int_regulator_en 12345678910111213141516 33 34 35 36 37 38 39 40 41 42 43 asix AX88178 17 18 19 20 44 45 46 47 21 22 23 24 25 48 49 50 51 52 53 54 55 56 57 26 27 28 29 30 31 32 58 110 109 108 107 106 103 104 105 117 116 115 114 111 112 113 124 123 122 121 118 119 120 128 125 126 127 59 60 61 62 63 64 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 102 101 98 99 100 97 dmrs gnd vddk vbus testspeedup nc forcefs_n extwakeup_n gndah vdd3 scan_test scan_enable clk60ext clksel vddk gnd eeck eecs eedi eedo vdd3 v25 agnd avdd3 tx_clk tx_en gtx_clk txc tx_er txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 gnd avddk xin125m rgmii_en agnd vdd3 gnd vdd2 agnd avddk db avddk agnd nc nc agnd nc nc nc nc vddk nc nc gnd vdd2 vdd2 rx_clk rx_dv rx_er rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs col gnd mdint mdc mdio gpio0 gpio1 gpio2 gnd vdd3 phyrst_n nc nc nc nc nc usb_speed_led led gnd vddk dp dm gnd gnd vddk reset_n vddah gnd gnd xin12m xout12m avdd3 agnd rref agnd rpu dprs avdd3 gnd vdd3 nc nc avddk agnd agnd avddk avddk agnd nc nc nc hs_test_mode
asix electronics corporation 5 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 2.0 signal description the following abbreviations apply to the following pin description table. i2 input, 2.5v with 3.3v tolerant b2 bi -directional i/o, 2.5v with 3.3v tolerant i3 input, 3.3v b5 bi-directiona l i/o, 3.3v with 5v tolerant i5 input, 3.3v with 5v tolerant pu internal pull up (75k) o2 output, 2.5v with 3.3v tolerant pd internal pull down (75k) o3 output, 3.3v p power pin o5 output, 3.3v with 5v tolerant s schmitt trigger b bi-directional i/o table 1: pinout descripton pin name type pin no pin description usb interface dp b 32 usb 2.0 data positive pin. dm b 31 usb 2.0 data negative pin. dprs b 36 usb 1.1 data positive pin. please connect to dp through a 39ohm (+/-1%) serial resistor. dmrs b 35 usb 1.1 data negative pin. please connect to dm through a 39ohm (+/-1%) serial resistor. vbus i5/pd/s 10 vbus pin input. please connect to usb bus power. xin12m i3 26 12mhz crystal or oscillator cl ock input. this clock is needed for usb phy transceiver to operate. xout12m o3 27 12mhz crystal or oscillator clock output. rref i 30 for usb phy?s internal biasing. please connect to agnd through a 12.1kohm (+/-1%) resistor. rpu i 34 for usb phy?s internal biasi ng. please connect to avdd3 (3.3v) through a 1.5kohm (+/-5%) resistor. station management interface mdc o2 121 station management data clock output. the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. the frequency of mdc is 1.5mhz. mdio b2/pu 120 station management data input/output. serial data input/output transfers from/to the phys. the tr ansfer protocol conforms to the ieee 802.3u mii spec. mdint i2/pu 117 station management interrupt input. mii/gmii/rgmii interface rx_clk i2 104 receive clock. rx _clk is received from phy to p rovide timing reference for the transfer of rxd [7:0], rx_dv, and rx_er signals on receive direction of mii/gmii/rgmii interface. rxd [7:0] i2 114, 113, 112, 111, 110, 109, 108, 107 receive data. rxd [7:0] is driv en synchronously with respect to rx_clk by phy. in rgmii mode, only rxd [3:0] is used. rx_dv i2 105 receive data valid. rx_dv is driven synchronously with respect to rx_clk by phy. it is asserted high when valid data is present on rxd [7:0]. in rgmii mode, rx_dv acts as rx_ctl. rx_er i2 106 receive error. rx_er is driven synchronously with respect to rx_clk by phy. it is asserted high for one or more rx_clk periods to indicate to the mac that an error has detected. col i2 116 collision detected. col is driven high by phy when the collision is detected. crs i2 115 carrier sense. crs is asserted high asynchronously b y the phy when either transmit or receive medium is non-idle.
asix electronics corporation 6 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller tx_clk i2 102 transmit clock in mii mode. tx_clk is received from phy to provide timing reference for the transfer of txd [3:0], tx_en and tx_er signals on transmit direction of mii interface. gtx_clk o2 91 transmit clock in gmii mode. gtx_clk is output to phy to provide timing reference for the transfer of txd [7:0], tx_en and tx_er signals on transmit direction of gmii interface. txc o2 90 transmit clock in rgmii mode. txc is output to phy to provide timing reference for the transfer of txd [3:0], and tx_en signals on transmit direction of rgmii interface. txd [7:0] o2 76, 77, 78, 79, 82, 83, 84, 85 transmit data. txd [7:0] is transitioned synchronously with respect to the rising edge of gtx_clk in gmii mode or rising edge of tx_clk in mii mode. in rgmii mode, only txd [3:0] is used and is transitioned synchronously with respect to txc clock output pin. tx_en o2 89 transmit enable. tx_en is transitioned synchronously with respect to the rising edge of gtx_clk in gmii mode or rising edge of tx_clk in mii mode. tx_en is asserted high to indicate a valid txd [7:0]. in rgmii mode, tx_en acts as tx_ctl and is transitioned synchronously with respect to txc clock output pin. tx_er o2 88 transmit coding error. tx_er is transitioned synchronously with respect to the rising edge of gtx_clk in gmii mode or rising edge of tx_clk in mii mode. when asserted high for one or more gtx_clk/tx_clk, the phy shall emit one or more code-groups that are not part of the valid data or delimiter set somewhere in the frame being transmitted. serial eeprom interface eeck o5 4 eeprom clock. eeck is an output clock to eeprom to provide timing reference for the transfer of eecs, eedi, and eedo signals. the frequency of eeck is 187.5khz. eecs o5 5 eeprom chip select. eecs is asserted high synchronously with respect to rising edge of eec k as chip select signal. eedi o5 6 eeprom data in. eedi is the serial output data to eeprom?s data input pin and is synchronous with respect to the rising edge of eeck. eedo i5/pd 9 eeprom data out. eedo is the serial input data from eeprom?s data output pin. misc. pins xin125m i2 101 125mhz clock input. connect to a 125mhz free run clock source when in gmii or rgmii mode. in mii mode, connect to gnd through a pull-down resistor. reset_n i5/pu/s 12 chip reset input. reset_n pin is active low. when asserted, it puts the entire chip into reset state immediately. after completing reset, eeprom data will be loaded automatically. extwakeup_n i5/pu/s 11 remote-wakeup trigger from external pin. extwakeup_n should be asserted low for more than 2 cycles of 12mhz clock to be effective. gpio [2:0] b5/pd 1, 2, 3 general purpose inpu t/ output pins. these pins are default as input pins after power-on reset. please use gpio0 for controlling the power down pin of external ethernet phy. phyrst_n o2 122 phyrst_n is a tri-stat eable output used for resetting external ethernet phy. this pin is default in tri-state after power-on reset. if external ethernet phy?s reset level is active low, connect this to phy?s reset pin with a pulled-down resistor. if it?s active high, connect this to phy with a pulled-up resistor. this way can make sure the external ethernet phy stays in re set state before software brings it out of reset. rgmii_en i3/pd 103 rgmii mode enable. setti ng this pin high sets the ethernet phy interface into rgmii mode. setting th is pin low sets the ethernet phy interface into mii or gmii mode.
asix electronics corporation 7 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller forcefs_n i3/pu 15 force usb full speed (active low). for normal operation, user should keep this pin nc to enable usb high speed handshaking process to decide the speed of usb bus. setting this pin low sets the device to operate at full speed mode only and disables chirp k (hs handshaking process). led o3 125 led indicator: when usb bus is in full speed, this pin drives high continuously. when usb bus is in high speed, this pin drives low continuously. this pin drives high and low in turn (blinking) to indicate tx data transfer going on whenever the host controller sends bulk out data transfer. usb_speed_le d o3 126 usb bus speed led indicator. when usb bus is in full speed, this pin drives high continuously. when usb bus is in high speed, this pin drives low continuously. testspeedup i3/pd 13 test pin. for normal operation, user should keep this pin nc. hs_test_mode i3/pd 42 test pin. for normal operation, user should keep this pin nc. scan_test i3/pd 43 test pin. for normal operation, user should keep this pin nc. scan_enable i3/pd 44 test pin. for normal operation, user should keep this pin nc. clk60ext i3/pd 45 test pin. for normal operation, user should keep this pin nc. clksel i3/pd 46 test pin. for normal operation, user should keep this pin nc. db i2 65 debug pin. for normal operation, user should connect to avddk through a pulled-up resistor. on-chip regulator pins int_regulato r_en i 20 on-chip 3.3v to 2.5v voltage regulator enable. connect this pin to vddah directly to enable on-chip regulator. connect this pin to gndah to disable on-chip regulator. vddah p 22 3.3v power supply to on-chip 3.3v to 2.5v voltage regulator. gndah p 23 ground pin of on-chip 3.3v to 2.5v voltage regulator. v25 p 21 2.5v voltage output of on-chip 3.3v to 2.5v voltage regulator. power and ground pins vddk p 16, 24, 74, 99, 118 digital core power. 2.5v. vdd2 p 80, 86, 123 digital i/o power. 2.5v. vdd3 p 8, 19, 41, 97, 128 digital i/o power. 3.3v. gnd p 7, 17, 18, 25, 40, 75, 81, 87, 98, 100, 119, 124, 127 digital ground. avddk p 49, 53, 57, 64, 66, 68 analog core power. 2.5v. avdd3 p 28, 37, 39 analog i/o power. 3.3v. agnd p 29, 33, 38, 50, 54, 55, 60, 63, 67, 69 analog ground.
asix electronics corporation 8 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 3.0 function description 3.1 usb core and interface the usb core and interface contains an usb 2.0 transcei ver, serial interface engine (sie), usb bus protocol handshaking block, usb standard command, vendor command registers, logic for supporting bulk transfer, and interrupt transfer, etc. the usb interface is used to communicate with usb host c ontroller and is compliant with usb specification v1.0, v1.1 and v2.0. 3.2 gigabit mac core the gigabit mac core supports ieee 802.3, 802.3u, and 802.3a b mac sub-layer functions, such as basic mac frame receive and transmit, crc checking and generation, filteri ng, forwarding, flow-contro l in full-duplex mode, and collision-detection and handling in hal f-duplex mode, etc. it pr ovides gigabit media-indepe ndent (gmii) and reduced gigabit media-independent (r gmii) interface for interfacing w ith gigabit ethernet phy. 3.3 station management (sta) the station management interface provides a simple, two-wire, serial interface to connect to a managed phy device for the purposes of controlling the phy and gathering status from the phy. the station management interface allows communicating with multiple phy devices at the same time by identifying the managed phy with 5-bit, unique phy id. 3.4 memory arbiter the memory arbiter block is responsible for storing received mac frames into on-chip sram (packet buffer) and then forwarding to usb bus upon request from usb host via bulk in transfer. it also monitors packet buffer usage in full-duplex mode for triggering pause frame transmission out on tx direction. the memory arbiter block is also responsible for storing mac frames received from usb host via bulk out transfer and wa iting to be transmitted out towards ethernet network. 3.5 usb to ethernet bridge the usb to ethernet bridge block is responsible for conve rting ethernet mac frame into usb packets or vice-versa. this block supports proprietary burst transfer mechanism (s ubmitted for us patent applica tion) to offload software burden and to offer very high packet transfer throughput over usb bus. 3.6 serial eeprom loader the serial eeprom loader is responsible for reading configuration data automatically from external serial eeprom after power-on reset. 3.7 general purpose i/o there are 3 general purpose i/o pins provided by this asic.
asix electronics corporation 9 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 4.0 serial eeprom memory map eeprom offset high byte low byte 00h reserved word count for preload 01h flag 02h length of high-speed device descriptor (bytes) eeprom offset of high-speed device descriptor 03h length of high-speed configuration descriptor (bytes) eeprom offset of high-speed configuration descriptor 04h node id 1 node id 0 05h node id 3 node id 2 06h node id 5 node id 4 07h language id high byte language id low byte 08h length of manufacture string (bytes) eeprom offset of manufacture string 09h length of product string (bytes) eeprom offset of product string 0ah length of serial number string (bytes) eeprom offset of serial number string 0bh length of configuration string (bytes) eeprom offset of configuration string 0ch length of interface 0 string (bytes ) eeprom offset of interface 0 string 0dh length of interface 1/0 string (bytes) eeprom offset of interface 1/0 string 0eh length of interface 1/1 string (bytes) eeprom offset of interface 1/1 string 0fh phy register offset for interrupt endpoint phy register offset for interrupt endpoint 10h max packet size high byte max packet size low byte 11h secondary phy_type [7:5] and phy_id [4:0] primary phy_type [7:5] and phy_id [4:0] 12h pause frame high water mark pause frame low water mark 13h length of full-speed device descriptor (bytes) eeprom offset of full-speed device descriptor 14h length of full-speed configuration descriptor (bytes) eeprom offset of full-speed configuration descriptor 15h-1fh reserved reserved table 2: serial eeprom memory map
asix electronics corporation 10 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 4.1 detailed description the following sections provide detailed description for some of the field in serial eeprom me mory map, for other fields not covered here, please refer to AX88178l application note for more details. 4.1.1 word count for preload (00h) the number of words to be preloaded by the eeprom loader = 15h. 4.1.2 flag (01h) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved tdpe cem bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tace rdce scpr dck 1 rwu reserved sp sp: self-power (for usb getstatus) 1: self power. 0: bus power. rwu: remote wakeup support. 1: indicate that this device supports remote wakeup. 0: not support. dck: disable chirp k. 1: disabled. 0: enable. scpr: software control phy reset. 1: the prl and prte bits of software reset register control the phyrst_n output level. 0: the usb reset on usb bus and prte bit of software reset register control the phyrst_n output level. rdce: rx drop crc enable. 1: crc byte is dropped on receive d mac frame forwarding to host. 0: crc byte is not dropped. tace: tx append crc enable. 1: crc byte is generated and appended by the asic for every transmitted mac frame. 0: crc byte is not appended. cem: capture effective mode. 1: capture effective mode enable. 0: disabled. tdpe: test debug port enable. 1: enable test debug port for chip debug purpose. 0: disable test debug port and the chip operate in normal function mode bit 1, 10~15: reserved. 4.1.3 node id (04~06h) the node id 0 to 5 bytes represent the mac address of the device, for example, if mac address = 01-23-45-67-89-abh, then node id 0 = 01, node id 1 = 23, node id 2 = 45, node id 3 = 67, node id 4 = 89, and node id 5 = ab.
asix electronics corporation 11 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 4.1.4 phy register offset for interrupt endpoint (0fh) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved phy register offset 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved phy register offset 2 phy register offset 1: fill in phy? s register offset of primary phy here . upon each interrupt endpoint issued, its register value will be reported in byte # 5 and 6 of interr upt endpoint packet. phy register offset 2: fill in phy?s register offset of primary phy here. upon each interrupt endpoint issued, its register value will be reported in byte # 7 and 8 of interr upt endpoint packet. 4.1.5 max packet size high/low byte (10h) fill in this field the maximum rx/tx mac frame size supported by this asic when jumbo frame mode is disabled. the number must be even number in terms of byte and should be less than or equal to 2500 bytes. when jumbo frame mode is enabled, the maximum mac frame size is fi xed to 9216 bytes and this setting is ignored. 4.1.6 primary/secondary phy_type and phy_id (11h) the 3 bits phy_type field for both primary and secondary phy is defined as follows, 3?b000: 10/100 ethernet phy or 1m home phy (link reports as normal case). 3?b100: special case 1 (link reports as always active). 3?b001: gigabit ethernet phy. 3?b111: non-supported phy. for example, the high byte value of ?e0h? in eeprom offset of ?11h? means that secondary phy is not supported. 4.1.7 pause frame high water and low water mark (12h) when operating in full-duplex mode, correct setting of this field is very importa nt and can affect the overall packet receive throughput performance in a great d eal. the high water mark is the thres hold to trigger sending of pause frame and the low water mark is the threshold to stop sending of pause frame. note that each free buffer count here represents 256 bytes of packet storage space in sram. when jumbo frame mode is not disabled, user can fill in a smaller value in high water mark and a larger value in low water mark fields to have more effici ent use of sram for packet buffering. total free buffer count = 80 start sendin g pause frame when free buffer < hi g h water mar k 0 sto p sendin g pause frame when free buffer > low water mar k
asix electronics corporation 12 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 4.1.8 power-up steps after power-on reset, the asic will automatically perform fo llowing steps to the ethernet phys via mdc/mdio lines, 1. write to phy_id of 00h with phy register offset 00h to power down all phys attached to station management interface. 2. write to primary phy_id with phy register offset 00h to power down primary phy. 3. write to secondary phy_id with phy register offset 00h to power down secondary phy.
asix electronics corporation 13 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 5.0 usb configuration structure 5.1 usb configuration the AX88178 supports 1 configuration only. 5.2 usb interface the AX88178 supports 2 interfaces, the interface 0 is data interface and interface 1 is for communication interface. 5.3 usb endpoints the AX88178 supports following 4 endpoints: endpoint 0: control endpoint. it is used for configuri ng the device, e.g., standard commands and vendor commands, etc. endpoint 1: interrupt endpoint. it is used for reporting status. endpoint 2: bulk out endpoi nt. it is used for tran smitting ethernet packet. endpoint 3: bulk in endpoi nt. it is used for r eceiving ethernet packet.
asix electronics corporation 14 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.0 usb commands there are three command groups for endpoint 0 (control endpoint) in AX88178: the usb standard commands the usb vendor commands the usb communication class commands 6.1 usb standard commands the language id is 0x0904 for english ppll means buffer length cc means configuration number i i means interface number aa means device address setup command data bytes access type description 8006_00 01 00 00 llpp ppll bytes in data stage read get device descriptor 8006_0002 0000_llpp ppll bytes in data stage read get configuration descriptor 8006_0003_0000_llpp ppll bytes in da ta stage read get supported language id 8006_0103_0904_llpp ppll bytes in data stage read get manufacture string 8006_0203_0904_llpp ppll bytes in data st age read get product string 8006_0303_0904_llpp ppll bytes in da ta stage read get serial number string 8006_0403_0904_llpp ppll bytes in data stage read get configuration string 8006_0503_0904_llpp ppll by tes in data stage read get interface 0 string 8006_0603_0904_llpp ppll by tes in data stage read get interface 1/0 string 8006_0703_0904_llpp ppll by tes in data stage read get interface 1/1 string 8008_0000_0000_0100 1 bytes in data stage read get configuration 0009_cc00_0000_0000 no data in data stage write set configuration 810a_0000 _i i00_0100 1 bytes in data stage read get interface 010b_as00_0000_0000 no data in data stage write set interface 0005_aa00_0000_0000 no data in data stage write set address table 3: usb standard command register map
asix electronics corporation 15 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2 usb vendor commands no setup command data bytes access type description 1. c002_aa0b_0c00_0800 8 bytes in data stage read rx /tx sram read register 2. 4003_aa0b_0c00_0800 8 bytes in data stage write rx/tx sram write register 3. 4006_0000_0000_0000 no data in data stage write software serial management control register 4. c007_ aa00_cc00_0200 2 bytes in data stage read phy read register 5. 4008 _aa00_cc00_0200 2 bytes in data stage write phy write register 6. c009_0000_0000_0100 1 bytes in data stage read se rial management status register 7. 400a_0000_0000_0000 no data in data stage write hardware serial management control register 8. c00b_aa00_0000_0200 2 bytes in data stage read srom read register 9. 400c_aa00_ccdd_0000 no data in data stage write srom write register 10. 400d_0000_0000_0000 no data in data stage write srom write enable register 11. 400e_0000_0000_0000 no data in data stage write srom write disable register 12. c00f_0000_0000_0200 2 bytes in data stage read rx control register 13. 4010_aabb_0000_0000 no data in data stage write rx control register 14. c011_0000_0000_0300 3 bytes in data stage read ipg/ipg1/ipg2 register 15. 4012_aabb_cc00_0000 no data in data stage write ipg/ipg1/ipg2 register 16. c013_0000_0000_0600 6 bytes in data stage read node id register 17. 4014_0000_0000_0600 6 bytes in data stage write node id register 18. c015_0000_0000_0800 8 bytes, ma0~ma7 , in data stage read multicast filter array register 19. 4016_0000_0000_0800 8 bytes, ma0~ma7 , in data stage write multicast filter array register 20. 4017_aa00_0000_0000 no data in data stage write test register 21. c019_0000_0000_0200 2 bytes in data stage read ethernet/homepna phy address register 22. c01a_0000_0000_0200 2 bytes in data stage read medium status register 23. 401b_aabb_0000 _0000 no data in data stage write medium mode register 24. c01c_0000_0000_0100 1bytes in data stage read monitor mode status register 25. 401d_aa00_0000_0000 no data in data stage write monitor mode register 26. c01e _0000_0000_0100 1 bytes in data stage read gpios status register 27. 401f_aa00_0000_0000 no data in data stage write gpios register 28. 4020_aa00_0000_0000 no data in data stage write software reset register table 4: usb vendor command register map
asix electronics corporation 16 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1 detailed register description 6.2.1.1 rx/tx sram read register (02h, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] reserved b [3:0] 0h c [3:0] dd [7:0] in data stage ee [7:0] in data stage ff [7:0] in data stage gg [7:0] in data stage hh [7:0] in data stage ii [7:0] in data stage jj [7:0] in data stage kk [7:0] in data stage {b [3:0], aa [7:0]}: the read address of rx or tx sram. c [0]: ram selection. 0: indicates to read from rx sram. 1: indicates to read from tx sram. c [3:1]: reserved. {dd [7:0], ee [7:0], ff [7:0], gg [7:0], hh [7:0], ii [7:0], jj [7:0], kk [7:0]}: the 64-bits of data presented in data stage are the data to be written to rx or tx sram. 6.2.1.2 rx/tx sram write register (03h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] reserved b [3:0] reserved c [3:0] dd [7:0] in data stage ee [7:0] in data stage ff [7:0] in data stage gg [7:0] in data stage hh [7:0] in data stage ii [7:0] in data stage jj [7:0] in data stage kk [7:0] in data stage {b [3:0], aa [7:0]}: the write address of rx or tx sram. c [0]: ram selection. 0: indicates to write to rx sram. 1: indicates to write to tx sram. c [3:1]: reserved. {dd [7:0], ee [7:0], ff [7:0], gg [7:0], hh [7:0], ii [7:0], jj [7:0], kk [7:0]}: the 64-bits of data presented in data stage are the data to be written to rx or tx sram. 6.2.1.3 software serial management c ontrol register (06h, write only) when software needs to access to ethernet phy?s internal registers, one has to first issue this command to request the ownership of serial manage ment interface. the ownership status of the interface can be retrieved from serial management status register.
asix electronics corporation 17 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1.4 phy read register (07h, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] 00h cc [7:0] aa [4:0]: the phy id value. cc [4:0]: the register address of ethernet phy?s internal register. aa [7:5]: reserved cc [7:5]: reserved 6.2.1.5 phy write register (08h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] 00h cc [7:0] aa [4:0]: the phy id value. cc [4:0]: the register address of ethernet phy?s internal register. aa [7:5]: reserved cc [7:5]: reserved 6.2.1.6 serial management status register (09h, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved host_en host_en: host access enable. software can read this register to determ ine the current ownership of serial management interface. 1: software is allowed to access ethern et phy?s internal registers via phy r ead register or phy write registers. 0: asic?s hardware owns the serial management interface and so ftware?s access is ignored. 6.2.1.7 hardware serial management c ontrol register (0ah, write only) when software is done accessing serial management interface, one needs to issue this command to release the ownership of the interface back to asic?s hardware. afte r issuing this command, follo wing phy read register or phy write register from software will be ignored. note : software should issue this command every time after finished accessing serial manage ment interface to release the ownership back to hardware to allow periodic interrupt endpoint to be able to access the ethernet phy?s registers via the serial management interface. 6.2.1.8 srom read register (0bh, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] aa [7:0]: the read address of serial eerom.
asix electronics corporation 18 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1.9 srom write register (0ch, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] 00h cc [7:0] dd [7:0] aa [7:0]: the write address of serial eerom. { dd [7:0], cc [7:0] }: the write data value of serial eerom 6.2.1.10 write srom enable (0dh, write only) user issues this command to enable write perm ission to serial eeprom from srom write register. 6.2.1.11 write srom disable (0eh, write only) user issues this command to disable write perm ission to serial eeprom from srom write register. 6.2.1.12 rx control register (0fh, read only and 10h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 so reserved ap am ab sep amall pro 0h reserved mfb [1:0] aa [7:0] = { so, reserved, ap, am, ab, reserved, amall, pro } bb [7:0] = { 0h, reserv ed [3:2], sb [1:0] } pro: packet_type_promiscuous. 1: all frames received by the asic are forwarded up toward the host. 0: disabled (default). amall: packet_type_all_multicast. 1: all multicast frames received by the asic are forw arded up toward the host, not just the frames whose scrambling result of da matching with multicast address list provided in multicast filter array register. 0: disabled. this only allows multicast frames whose scrambling result of da field matching with multicast address list provided in multicast filter array register to be forwarded up toward the host (default). sep: save error packet. 1: received packets with crc error ar e saved and forwarded to the host anyway. 0: received packets with crc error are discarded auto matically without forwardi ng to the host (default). ab: packet_type_broadcast. 1: all broadcast frames received by the asic are forwarded up toward the host (default). 0: disabled. am: packet_type_multicast. 1: all multicast frames whose scrambling result of da matching with multicast address list are forwarded up to the host (default). 0: disabled. ap: accept physical address from multicast filter array. 1: allow unicast packets to be forwarded up toward host if the lookup of scrambling result of da is found within multicast address list. 0: disabled, that is, unicast pack ets filtering are done without regard ing multicast address list (default). so: start operation. 1: cactus start. 0: cactus stop (default).
asix electronics corporation 19 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller mfb [1:0]: maximum frame burst transfer on usb bus. 00: 2048 bytes 01: 4096 bytes 10: 8192 bytes 11: 16384 bytes (default). user should set to this value when jumbo packet mode is enabled to gain better transfer throughput on usb bus. 6.2.1.13 ipg/ipg1/ipg2 control register (11h, read only and 12h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] bb [7:0] cc [7:0] aa [6:0] = ipg [6:0]. bb [6:0] = ipg1 [6:0]. cc [6:0] = ipg2 [6:0]. ipg [6:0]: inter packet gap for back-to-back transfer on tx direction in mii mode (default = 15h). ipg1 [6:0]: ipg part1 value (default = 0ch). ipg2 [6:0]: ipg part1 value + part2 value (default = 12h). aa [7]: reserved. bb [7]: reserved. cc [7]: reserved. 6.2.1.14 node id register (13h, read only and 14h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 aa [7:0] bb [7:0] cc [7:0] dd [7:0] ee [7:0] ff [7:0] aa [7:0] = noid 0. bb [7:0] = noid 1. cc [7:0] = noid 2. dd [7:0] = noid 3. ee [7:0] = noid 4. ff [7:0] = noid 5. {ff [7:0], ee [7:0], dd [7:0], cc [7:0], bb [7:0], aa [7:0]} = ethernet mac address [47:0] of the node.
asix electronics corporation 20 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1.15 multicast filter array (15h, read only and 16h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ma 0 [7:0] ma 1 [7:0] ma 2 [7:0] ma 3 [7:0] ma 4 [7:0] ma 5 [7:0] ma 6 [7:0] ma 7 [7:0] {ma7 [7:0], ma6 [7:0], ma5 [7:0], ma4 [7:0], ma3 [7 :0], ma2 [7:0], ma1 [7:0], ma0 [7:0]} = the multicast address bit map for multicast frame filtering block. see figure 3: multicast filter example, for example. figure 3: multicast filter example 6.2.1.16 test register (17h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mm [7:6] ldrnd ldrnd: load random number into mac?s exponential back-off timer. user writes a ?1? to enable the asic to load a small random number into mac?s back-off timer to shorten the back-off duration in each retry after collision. this register is used for test purpose. default value = 0. mm [7:6]: reserved. 6.2.1.17 ethernet / homepna phy address register (19h, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 secphytype [2:0] secphyid [4:0] priphytype [2:0] priphyid [4:0] secphytype, secphyid: the secondary phy address loaded from serial eeprom?s offset address 11h. priphytype, priphyid: the primarily phy address loaded from serial eeprom?s offset address 11h. da 81 81 81 81 81 81 crc32 {crc31, 30, 29, 28, 27, 26} mar[63:0] = 400_0000h address[5:0] = 1ah
asix electronics corporation 21 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1.18 medium status register (1ah, read only) and medium mode register (1bh, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pf jfe tfc rfc enck ac fd gm reserved sm sbp reserved ps re aa [7:0] = {pf, jfe, tfc, rfc, en125, ac, fd, gm}. bb [7:0] = {reserved, sm, sbp, je, ps, re}. gm: gigabit mode. 1: gmii mode. 0: mii mode (default). ps: port speed in mii mode 1: 100 mbps (default). 0: 10 mbps. {gm, ps} rgm ii/mii/gmii port speed selection 00: 10mbps 01: 100mbps 10: 1000mbps 11: 1000mbps fd: full duplex mode 1: full duplex mode (default). 0: half duplex mode. ac: reserved bit. for normal operation, please always write 1 to this bit. enck: enable gtx_clk and txc clock outputs 1: enable. 0: disabled (default). enck rgmii_en gtx_clk txc 0 0 off off 0 1 off off 1 0 on off 1 1 off on rfc: rx flow control enable. 1: enable receiving of pause frame on rx direction during full duplex mode (default). 0: disabled. tfc: tx flow control enable. 1: enable transmitting pause frame on tx direction during full duplex mode (default). 0: disabled. jfe: jumbo frame enable. 1: enable the support of jumbo frame in gigabit mode (default). 0: disabled. pf: check only ?length/typ e? field for pause frame. 1: enable, i.e., pause frames are identified only based on l/t filed. 0: disabled, i.e., pause frames are identified based on both da and l/t fields (default). re: receive enable. 1: enable rx path of the asic. 0: disabled (default). sbp: stop backpressure. 1: when tfc bit = 1, setting this bit enables backpressure on tx direction ?continuously? during rx buffer full condition in half duplex mode. 0: when tfc bit = 1, setting this bit enable backpressure on tx direction ?intermittently? during rx buffer full condition in half duplex mode (default). sm: super mac support. 1: enable super mac to shorten exponential back-off time during transmit retry. 0: disabled (default).
asix electronics corporation 22 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1.19 monitor mode status register (1ch, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved us reserved rwmp rwlu mom mom: monitor mode. 1: enable. all received packets will be ch ecked on da and crc but not buffered into memory. 0: disabled (default). rwlu: remote wakeup trigger by ethernet link-up. 1: enable 0: disabled (default). rwmp: remote wakeup trigger by magic packet. 1: enable 0: disabled (default). us: usb speed. 1: high speed mode. 0: fs speed mode. 6.2.1.20 monitor mode register (1dh, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved rwmp rwlu mom mom: monitor mode. 1: enable. all received packets will be ch ecked on da and crc but not buffered into memory. 0: disabled (default). rwlu: remote wakeup trigger by ethernet link-up. 1: enable. 0: disabled (default). rwmp: remote wakeup trigger by magic packet. 1: enable. 0: disabled (default). aa [7:3]: reserved. 6.2.1.21 gpio status register (1eh, read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gpi_2 gpo_2_en gpi_1 gpo_1_en gpi_0 gpo_0_en gpo_0_en: current level of pin gpio0?s output enable. gpi_0: input level on gpio0 pin when gpio0 is as an input pin. gpo_1_en: current level of pin gpio1?s output enable. gpi_1: input level on gpio1 pin when gpio1 is as an input pin. gpo_2_en: current level of pin gpio2?s output enable. gpi_2: input level on gpio2 pin when gpio2 is as an input pin.
asix electronics corporation 23 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.1.22 gpio register (1fh, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rse reserved gpo_2 gpo2en gpo_1 gpo1en gpo_0 gpo0en gpo0en: pin gpio0 output enable. 1: output is enabled (meaning gpio0 is used as an output pin). 0: output is tri-stated (meaning gpio0 is used as an input pin) (default). gpo_0: pin gpio0 output value. gpo1en: pin gpio1 output enable. 1: output is enabled (meaning gpio1 is used as an output pin). 0: output is tri-stated (meaning gpio1 is used as an input pin) (default). gpo_1: pin gpio1 output value. 0: (default). gpo2en: pin gpio2 output enable. 1: output is enabled (meaning gpio2 is used as an output pin). 0: output is tri-stated (meaning gpio2 is used as an input pin) (default). gpo_2: pin gpio2 output value. 0: (default). rse: reload serial eeprom. 1: enable. 0: disabled (default) 6.2.1.23 software reset register (20h, write only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 1 0 bz prl prte rt rr rr: clear frame length error for bulk in. 1: set high to clear state. 0: set low to exit clear state (default). rt: clear frame length error for bulk out. 1: set high to enter clear state. 0: set low to exit clear state (default). prte: external phy reset pin tri-state enable. 1: enable, i.e., the external phyrst_n pin is tri-stated (default). this allows the phyrst_n pin?s active level to be controlled by external pulled-up (active high during power-on) or pulled-down resistor (active low during power-on). 0: disabled, i.e., the external phyrst_n pin?s level is driven by either prl bit or internal ?usb reset? based on the setting in scpr bit in flag byte of eeprom. prl: external phy reset pin level. when scpr bit = 1 and prte = 0, this bit controls the output level of external phyrst_n pin. 1: set to high (default). 0: set to low. bz: force bulk in to re turn a zero-length packet. 1: software can force bulk in to return a zero-length usb packet. 0: normal operation mode (default). bit [7:5]: please always write 010 to these bits.
asix electronics corporation 24 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 6.2.2 remote wakeup description after AX88178 enters into suspend mode, either the usb host or AX88178 itself can awake it up and resume back to the original operation mode before it entered suspend. following truth table shows the chip setting, wakeup event, and device response supported by this asic. note that ?x? stands for don?t-care. setting wakeup event device awakes up? wakeup by rwu bit of flag byte in eepro m set_feature standard command rwlu of monitor mode register rwmp of monitor mode register host send resume signal receiving magic packet extwake up_n pin linkup detected on primary phy linkup detected on secondary phy host x x x x j -> k yes device 0 0 x x x x x x no device 1 1 0 1 yes yes device 1 1 1 0 yes yes device 1 1 1 0 yes yes device 1 1 x x low-pulse yes table 5: remote wakeup truth table 6.3 interrupt endpoint the interrupt endpoint contains 8 bytes of data and its frame format is defined as: a100_bb00_ccdd_eeff. where bb byte in byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved mdint fle spls ppls ppls: primarily phy link state. 1: link is up. 0: link is down. spls: secondary phy link state. 1: link is up. 0: link is down. fle: bulk out ethernet frame length error. 1: proprietary length field has parity error during bulk out transaction. 0: proprietary length field has no parity error during bulk out transaction. mdint: input level of mdint pin. the mdint pin can be connectted to mdint# pin of ethernet phy. 1: when mdint input pin = 1. 0: when mdint input pin = 0. ccdd byte in byte 5 and 6: primary phy?s register value, whose offset is given in high byte of eeprom offset 0fh. eeff byte in byte 7 and 8: primary phy?s register value, whose offset is given in low byte of eeprom offset 0fh.
asix electronics corporation 25 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 7.0 electrical specifications 7.1 dc characteristics 7.1.1 absolute maximum ratings symbol parameter rating unit vddk digital core power supply - 0.3 to vddk + 0.3 v vdd2 power supply of 2.5v i/o - 0.3 to vdd2 + 0.3 v vdd3 power supply of 3.3v i/o - 0.5 to vdd3 + 0.5 v avddk analog core power supply - 0.3 to avddk + 0.3 v avdd3 power supply of analog i/o - 0.5 to avdd3 + 0.5 v input voltage of 2.5v i/o - 0.3 to vdd2 + 0.3 v v in2 input voltage of 2.5v i/o with 3.3v tolerant - 0.3 to 3.9 v input voltage of 3.3v i/o - 0.3 to vdd3 + 0.3 v v in3 input voltage of 3.3v i/o with 5v tolerant - 0.3 to 5.5 v t stg storage temperature - 40 to 150 note: permanent device damage may occu r if absolute maximum ratings are exceeded. functional operation should be restricted in the optional sections of this datasheet. exposure to absolute ma ximum rating condition for extended periods may affect device reliability. 7.1.2 recommended operating condition symbol parameter min typ max unit vddk digital core power supply 2.25 2.5 2.75 v vdd2 power supply of 2.5v i/o 2.25 2.5 2.75 v vdd3 power supply of 3.3v i/o 3.0 3.3 3.6 v avddk analog core power supply 2.25 2.5 2.75 v avdd3 power supply of analog i/o 3.0 3.3 3.6 v input voltage of 2.5 v i/o 0 2.5 2.75 v v in2 input voltage of 2.5 v i/o with 3.3 v tolerance 0 2.5 3.6 v input voltage of 3.3 v i/o 0 3.3 3.6 v v in3 input voltage of 3.3 v i/o with 5 v tolerance 0 3.3 5.25 v t j commercial junction operating temperature 0 - 115 7.1.3 leakage current and capacitance symbol parameter condition min typ max unit i in input current no pull-up or pull-down -10 1 10 a i oz tri-state leakage current -10 1 10 a c in input capacitance - 3.1 - pf c out output capacitance - 3.1 - pf c bid bi-directional buffer capacitance - 3.1 - pf
asix electronics corporation 26 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller note: the capacitance listed above does not include pad cap acitance and package capacitance. one can estimate pin capacitance by adding a pad capacitance of about 0.5pf and the package capacitance. 7.1.4 dc characteristics of 2.5v i/o pins symbol parameter condition min typ max unit vdd2 power supply of 2.5v i/o 2.25 2.5 2.75 v temp junction temperature 0 25 115 vil input low voltage - - 0.7 v vih input high voltage cmos 1.7 - - v vt- schmitt trigger negative going threshold voltage 0.7 1.0 - v vt+ schmitt trigger positive going threshold voltage cmos - 1.5 1.7 v vol output low voltage |iol| = 2~16ma - - 0.4 v voh output high voltage |ioh| = 2~16ma 1.85 - - v rpu input pull-up resistance 40 75 190 k rpd input pull-down resistance 40 75 190 k iin input leakage current vin = vdd2 or 0 -10 1 10 a ioz tri-state output leakage current -10 1 10 a 7.1.5 dc characteristics of 3.3v i/o pins symbol parameter condition min typ max unit vdd3 power supply of 3.3v i/o 3.3v i/o 3.0 3.3 3.6 v temp junction temperature 0 25 115 vil input low voltage - - 0.8 v vih input high voltage lvttl 2.0 - - v vt- schmitt trigger negative going threshold voltage 0.8 1.1 - v vt+ schmitt trigger positive going threshold voltage lvttl - 1.6 2.0 v vol output low voltage |iol| = 2~16ma - - 0.4 v voh output high voltage |ioh| = 2~16ma 2.4 - - v rpu input pull-up resistance 40 75 190 k rpd input pull-down resistance 40 75 190 k iin input leakage current vin = vdd3 or 0 -10 1 10 a ioz tri-state output leakage current -10 1 10 a 7.2 power consumption symbol description condition min typ max units i vddk2 current consumption of vddk/vdd2, 2.5v - 48.3 - ma i vdd3 current consumption of vdd3, 3.3v - < 1 - ma i avddk current consumption of avddk, 2.5v - < 2 - ma i avdd3 current consumption of avdd3, 3.3v operating at ethernet 1000mbps full duplex mode and usb high speed mode - 51.1 - ma
asix electronics corporation 27 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 7.3 ac timing characteristics 7.3.1 clock timing 7.3.1.1 xin12m t p_xin12m t h_xin12m t l_xin12m t r_xin12m t f_xin12m symbol parameter condition min typ max unit t p_xin12m xin12m clock cycle time - 83.33 - ns t h_xin12m xin12m clock high time - 41.6 - ns t l_xin12m xin12m clock low time - 41.6 - ns t r_xin12m xin12m rise time v il (max) to v ih (min) - - 1.0 ns t f_xin12m xin12m fall time v ih (min) to v il (max) - - 1.0 ns 7.3.1.2 xin125m t p_xin125m t h_xin125m t l_xin125m t r_xin125m t f_xin125m symbol parameter condition min typ max unit t p_xin125m xin125m clock cycle time 7.5 8.0 8.5 ns t h_xin125m xin125m clock high time 2.5 4.0 - ns t l_xin125m xin125m clock low time 2.5 4.0 - ns t r_xin125m xin125m rise time v il (max) to v ih (min) - - 1.0 ns t f_xin125m xin125m fall time v ih (min) to v il (max) - - 1.0 ns v ih v il v ih v il
asix electronics corporation 28 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 7.3.2 reset timing xin12m reset_n symbol description min typ max units trst reset pulse width (6ms ~10ms) after xin12m is running 72000 - - xin12m clock cycle 7.3.3 gmii timing (1000mbps) ttclk ttch ttcl gtx_clk tts tth txd [7:0] tx_en, tx_er symbol description min typ max units ttclk gtx_clk clock cycle time 7.5 8.0 8.5 ns ttch gtx_clk clock high time 2.5 4.0 - ns ttcl gtx_clk clock low time 2.5 4.0 - ns tts txd [7:0], tx_en, tx_er setup time 4.0 - - ns tth txd [:0], tx_en, tx_er hold time 0.5 - - ns trclk trch trcl rx_clk trs trh rxd [7:0] rx_dv, rx_er symbol description min typ max units trclk rx_clk clock cycle time 7.5 8.0 8.5 ns trch rx_clk clock high time 2.5 4.0 - ns trcl rx_clk clock low time 2.5 4.0 - ns trs rxd [7:0], rx_dv, and rx_er setup time 2.0 - - ns trh rxd [7:0], rx_dv, and rx_er hold time 0.0 - - ns trs t
asix electronics corporation 29 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 7.3.4 rgmii timing ttclk ttch ttcl txc t skew t t skew t txd [3:0] tx_en (tx_ctl) txc txd [3:0], tx_en (tx_ctl) trclk trch trcl rx_clk (rxc) rxd [3:0] rx_dv (rx_ctl) symbol description min typ max units ttclk txc clock cycle time at 1000mbps *1 7.2 8.0 8.8 ns ttch txc clock high time at 1000mbps *2 - 4.0 - ns ttcl txc clock low time at 1000mbps *2 - 4.0 - ns t skew t txc clock to txd [3:0] and tx_en output skew (at transmitter) -500 - 500 ps trclk rx_clk (rxc) clock cy cle ime at 1000mbps *1 7.2 8.0 8.8 ns trch rx_clk (rxc) clock high time at 1000mbps *2 - 4.0 - ns trcl rx_clk (rxc) clock low time at 1000mbps *2 - 4.0 - ns trsu rxd [3:0] and rx_dv (rx_ctl) to rx_clk (rxc) clock setup time 1.0 - - ns trhd rxd [3:0] and rx_dv (rx_ctl) to rx_clk (rxc) clock hold time 1.0 - - ns *1: for 10mbps and 100mbps, ttclk and trclk shall s cale to 400ns+/-40ns and 40ns+/-4ns respectively. *2: for 10mbps and 100mbps, the typical value of ttch, ttcl, trch, and trcl shall scale to 200ns and 20ns respectively. trsu trhd trsu trhd rxd [3:0] rxd [7:4] rx_dv rx_er txd [3:0] txd [7:4] tx_en tx_er < 500 p s < 500 p s < 500 p s < 500 p s
asix electronics corporation 30 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 7.3.5 mii timing (100mbps) ttclk ttch ttcl tx_clk tts tth txd [3:0] tx_en, tx_er symbol description min typ max units ttclk tx_clk clock cycle time *1 - 40.0 - ns ttch tx_clk clock high time *2 - 20.0 - ns ttcl tx_clk clock low time *2 - 20.0 - ns tts txd [3:0], tx_en, tx_er setup time 28.0 - - ns tth txd [3:0], tx_en, tx_er hold time 5.0 - - ns trclk trch trcl rx_clk trs trh rxd [3:0] rx_dv, rx_er symbol description min typ max units trclk rx_clk clock cycle time *1 - 40.0 - ns trch rx_clk clock high time *2 - 20.0 - ns trcl rx_clk clock low time *2 - 20.0 - ns trs rxd [3:0], rx_dv, and rx_er setup time 3.0 - - ns trh rxd [3:0], rx_dv, and rx_er hold time 0.5 - - ns *1: for 10mbps, the typical value of ttclk and trclk shall scale to 400ns. *2: for 10mbps, the typical value of ttch, ttcl, trch, and trcl shall scale to 200ns.
asix electronics corporation 31 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 7.3.6 station management timing mdc mdio (as output) mdio (as input) symbol description min typ max units tclk mdc clock cycle time - 666 - ns tch mdc clock high time - 333 - ns tcl mdc clock low time - 333 - ns tod mdc clock falling edge to mdio output delay 0 - 2 ns ts mdio data input setup time 10 - - ns th mdio data input hold time 0 - - ns 7.3.7 serial eeprom timing eeck eedi (output) eecs eedo (input) symbol description min typ max units tclk eeck clock cycle time - 5333 - ns tch eeck clock high time - 2666 - ns tcl eeck clock low time - 2666 - ns tdv eedi output valid to eeck rising edge time 2666 - - ns tod eeck rising edge to eedi output delay time 2666 - - ns tscs eecs output valid to eeck rising edge time 2666 - - ns thcs eeck falling edge to eecs invalid time 0 - - ns tlcs minimum eecs low time 23904 - - ns ts eedo input setup time 10 - - ns th eedo input hold time 100 - - ns tch tclk tcl valid valid tdv tod tscs thcs tlcs th data valid ts to d tclk ts th tch tcl
asix electronics corporation 32 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 8.0 package information b e d hd e he pin 1 a2 a1 l l1 a milimeter symbol min typ max a1 0.05 - - a2 1.35 1.40 1.45 a - - 1.60 b 0.13 0.18 0.23 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e - 0.4 bsc - hd 15.85 16.00 16.15 he 15.85 16.00 16.15 l 0.45 0.60 0.75 l1 - 1.00 ref - 0 3.5 7
asix electronics corporation 33 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller 9.0 ordering information AX88178 l f product name package lqfp f: lead free appendix a: system applications some typical applications fo r AX88178 are illustrated bellow. a.1 usb to gigabit ethernet converter
asix electronics corporation 34 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller a.2 usb to gigabit ethernet and/or homelan combo solution AX88178 10/100/1000 ethernet phy magnetic rj45 usb i/f eeprom AX88178 10/100/1000 mbps ethernet phy magnetic rj45 usb i/f eeprom home lan phy magnetic rj11
35 AX88178 l usb to 10/100/1000 gigabit ethernet/homepna controller revision history 4f, no.8, hsin ann rd., science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-5799500 fax: 886-3-5799558 email: support@asix.com.tw web: http://www.asix.com.tw revision date comment v 0.1 1/5/04 initial release. v 0.2 4/16/04 a dded power consumpti on data and updated pin description for pin usb_speed_led.

▲Up To Search▲

Price & Availability of AX88178

	To Download AX88178 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .